Components in SON-type packages — including VSON and WSON variants — are increasingly common in modern designs. While datasheets typically provide example footprints and solder paste stencil patterns, following these recommendations exactly often leads to suboptimal results.
In practice, using the default geometry can result in capillary solder wicking and even component lifting during reflow. As a consequence, the solder-wetting indicators may remain unconnected. This clearly shows that the manufacturer’s footprint and stencil design should be treated as a starting point rather than an optimized solution for a specific PCB layout or assembly process.
Most datasheets assume a stencil thickness of 0.125 mm. However, challenges arise when the same PCB includes fine-pitch components such as DSBGA devices — for example TPS22916CYFPR with a 0.4 mm pitch — which typically require a thinner stencil of 0.1 mm. In such cases, applying a 0.125 mm stencil is not practical.
As a result, both the VSON footprint and the stencil aperture design must be adapted to enable the use of a 0.1 mm stencil without introducing risks such as component lifting or unreliable solder joints.
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